The present invention relates to a semiconductor chip-mounting technique. More specifically, the present invention relates to a semiconductor chip-mounting structure using a low-dielectric constant (low-κ) material and a manufacturing method therefor.
In recent years, as the performance of semiconductor chips has increased, low-κ materials have come to be used in interlayer insulating films. However, because these materials are porous, they are very brittle and the mechanical stress due to warping caused by the difference in thermal expansion coefficients between a chip and a chip support during mounting causes these materials to become destroyed.
An overview of this problem is shown in FIGS. 1(a) and 1(b). FIG. 1(a) shows the situation during solder connection at the solder solidification temperature and FIG. 1(b) shows the situation during the cooling process. The chip support 11, which has a higher thermal expansion coefficient than the chip 12, is bowed during solder connection and is warped in the opposite direction during the cooling process. The joined portion 10 of a solder bump 13 is enlarged and shown to the right. In the enlarged joined portion 10 a low-κ layer 15 is formed on top of the semiconductor substrate 14 and a wiring layer 16 is formed on the low-κ layer 15. A solder bump 13 is connected to the wiring layer 16 via a barrier layer 17 (such as barrier metal). The mechanical stress due to warping caused by the difference in thermal expansion coefficients between the chip support 11 and the chip 12 causes peeling 18 of the wiring layer 16 connected to the solder bump 13 and peeling of the low-κ layer 15.
As the performance and functionality of semiconductor chips increases, higher currents flow through chips and reliability faults (open defects) occur in the electrode joints due to the electromigration (EM) phenomenon. An early solution to this problem has been to use a solder bump structure including a copper post, such as a column-shaped copper pillar or a platform-shaped copper pedestal. An overview of this solder bump structure is shown in FIGS. 2(a)-2(c).
FIG. 2(a) shows the C4 (controlled collapse chip connection) structure that is currently in use. A low-κ layer 15 is formed on top of a semiconductor substrate 14 and a protective layer 22 is formed on top of the low-κ layer 15. A solder bump 13 is connected via a UBM (under bump metallurgy) layer 21 to an electrode formed on top of the low-κ layer 15.
FIG. 2(b) shows a solder bump structure including a copper pillar. The copper pillar 24 is formed on top of a UBM layer 21 and the copper pillar 24 is connected via the UBM layer 21 to an electrode 23 formed on top of the low-κ layer 15.
FIG. 2(c) shows a solder bump structure including a copper pedestal. The copper pedestal 25 is formed on top of a UBM layer 21 and the copper pedestal 25 is connected via the UBM layer 21 to an electrode 23 formed on top of the low-κ layer 15. A solder bump 13 is formed on top of the copper pedestal 25.
In solder bump structures (b) and (c) having copper posts, the hardness of the bump is increased. As a result, the stress added to the low-κ layer 15 made of a material with a low dielectric constant is greater than in a conventional structure (a) made of solder alone. This makes defects such as peeling of the low-κ layer 15 more likely during mounting.
A method for reducing the stress added to a low-κ layer has been proposed, as shown in FIG. 3, in which the thickness of the protective layer 32 supporting the UBM layer 31 underneath the copper post 33 has been increased. However, it is difficult to form the UBM layer 31 when the thickness of the protective layer 32 is increased, so this proposed method entails manufacturing problems.
In the prior art, rewiring so as to electrically connect a semiconductor element arranged beneath a bump electrode is configured using a plating method and the rewiring is covered with a surface-protecting film.